As part of the verification process for circuit design, it is useful to use assertions. Assertions are Boolean expressions reflecting the constraints on the circuit's outputs. During a simulation testing the functionality of a circuit, assertions may detect defects whose effects are not necessarily propagated to a primary output. Effective use of assertions implies that a set of assertions is sufficient to cover the functionality of the circuit logic as defined by the register-transfer level (RTL). It is further useful to define an assertion density metric, to ensure that a set of assertions sufficiently covers the functionality of the circuit logic.
There are two primary methods of measuring assertion density. The first is known as Cone of Influence (COI). In this method the assertion is defined by the number of logic gates affected, and it is desired that the assertion will effect a large as possible number of logic gates. A cone is thus defined with a tip originating at the output and a base at the first available register. The second method is known as Minimal Sequential Depth (MSD). MSD uses COI; however, the MSD is defined by the number of registers within the cone. It is desired to have a high as possible COI and low as possible MSD. The higher the COI or lower the MSD, the better the assertion is. It is of note that both methods are syntax-based and do not reflect functionality.
It is therefore further noted that the prior art does not provide an effective way of measurement of assertion density which is required in order to satisfactorily ascertain that a circuit is well-enough covered. Providing such a method within a system for design and verification of integrated circuit would be advantageous.